1. Technical Field
The present invention relates to semiconductor devices and fabrication, and more particularly to methods and devices having nanowires or nanodots formed by stress-induced cracking.
2. Description of the Related Art
Nanowires are fabricated to increase surface area relative to volume in many applications, such as, in applications where absorption of radiation is of interest. Conventional methods for fabricating nanowires (NWs) may include different forms of lithography (e.g., E-beam lithography, photolithography, etc.). While effective, these processes are expensive and difficult to control, especially for sizes less than 20 nm. In addition to being cost-inefficient, lithography is extremely low throughput and prone to line-edge roughness, which results in a large scattering effect for carrier transport. Also, damage from dry etching processes leads to surface defects in the nanowires.
Another process includes VLS (vapor-liquid-solid) growth. VLS growth suffers from many issues, e.g., it is difficult to control the density of the nanowires and there is no alignment among the nanowires. In addition, VLS growth results in poor uniformity of material properties (dimensions and crystallinity). The nanowires are random and vertical, and the crystal quality is less than a Czochralski (CZ) single crystal, which leads to high defect density.